综述：垂直型集成电子器件的新机遇

图文导读

Fig. 1 Overview of 3D integration based on emerging materials， including organic semiconductors， metal oxide semiconductors， and 2D materials

Fig. 2 a Via-hole-based and b via-hole-less metal interconnection schemes for vertical integration to improve the integration density

Fig. 3 a Advantages obtained by using fuoropolymer or parylene as a protective layer in organic material-based vertical integration. b Schematic diagram realizing vertical stacking by applying FEP as a protective layer before forming an isolation layer. c Shift of the transfer curve by annealing after FEP deposition and PMMA coating. d Schematic diagram of a vertically stacked inverter with a structure that shares a gate composed of a blend semiconductor (TIPS-pentacene/PTAA) and PCBM with CYTOP as a protective layer. e Voltage transfer characteristics of the inverter. f Illustration of the process of deposition of parylene through the CVD method. g， h Schematic diagram and optical microscopy image of ultra-thin organic vertically stacked complementary inverter using parylene as gate dielectric and substrate. i A schematic diagram of an organic vertical stacking inverter in which all processes except parylene used as the gate dielectric was implemented by ink jet printing. j The transfer curves of the P(NDI2OD-T2) OTFT and diF-TES-ADT/PS OTFT

Fig. 4 a Schematic diagram of a complementary inverter in which a p-type copper oxide transistor is vertically stacked on top of an n-type α-IGZO transistor. b Transfer curve of CuO TFT when CuO thickness is 10， 20， and 30 nm. c Voltage transfer characteristics of a vertically stacked inverter composed of a copper oxide transistor and an α-IGZO transistor. d A schematic of vertically stacked complementary inverter composed of a p-type SnO and an n-type IGZO TFTs. e Voltage transfer characteristics of a complementary inverter in which n-type IGZO TFT and p-type SnO TFT are vertically stacked when VDD is 6， 8， and 10 V. f Change in the inverter characteristics according to red， green， and blue light application. g Optical image and cross-sectional schematic of vertically stacked metal oxide TFT arrays for high-resolution active-matrix organic light-emitting diode backplanes. h PBTS measurement results for switching and driving TFTs， which are the frst and second TFT layers for the backplane realization of high-resolution TFTs.

Fig. 5 Schematic diagram of a vertical stacked p-type organic semiconductor and n-type metal oxide hybrid inverter capable of complementary operation

Fig. 6 a Schematic diagram of a vertically stacked inverter with a structure in which the F8T2 TFT and the IGZO TFT share a gate electrode.b Output curves of the F8T2 TFT and IGZO TFT. c Voltage transfer characteristics of the vertically stacked organic-metal oxide hybrid inverter. d Schematic diagram of the vertically stacked organic-metal oxide hybrid inverter composed of IGZO TFT and pentacene TFT. e， f Voltage transfer characteristics and DC gain profles of IGZO-pentacene vertically stacked inverters at VDD of 4， 5， and 6 V. g Schematic device structure of a vertically stacked complementary inverter based on vertical Schottky barrier transistors composed of pentacene and IGZO. h， i Realization of inverter characteristics by controlling the Schottky barrier of junction between pentacene and graphene， IGZO and graphene through Fermi level modulation of graphene

Fig. 7 a Two-layer MoS2 TFTs manufacturing process through MOCVD process and optical microscope image of fabricated device and output curve characteristics of MoS2 TFT located on each layer. b Schematic diagram of vertically stacked multi-channel MoS2 FET structure to improve current driving capability through efective channel length reduction. c Illustration of a vertically stacked structure of three MoS2 TFTs， all layers of which are composed of 2D materials. d， e Current in output curve and transfer curve increasing with the number of vertically integrated MoS2 channels

Fig. 8 a Illustration of a vertically stacked inverter based on vertical transistors composed of MoS2 and Bi2Sr2Co2O8. b A schematic diagram of a vertically stacked inverter with a structure in which n-type MOS2 TFT and p-type WSe2 TFT share a gate. c Voltage transfer characteristics of the vertically stacked inverter. d， e Schematic and optical microscopy images of the thermal deposited Te TFT-based vertically stacked inverter structures. f Voltage transfer characteristics of Te-based vertically stacked inverter. g Circuit diagram of differential amplifier (bottom layer) and common source amplifier (top layer) designed using MoS2 and WSe2. h Output of differential amplifier (bottom layer) and common source amplifier (top layer) circuit for an input signal with a peak-to-peak voltage of 50 mV.

Fig. 9 a Schematic diagram of a monolithic 3D image sensor with a monolayer TMD phototransistor array integrated on Si nanowire FET[1]based logic/memory hybrid 3D integrated circuits. b Back-end-of-line CMOS integration of CVD graphene with 388×288 pixel image sensor read-out circuit. c Schematic diagram in which various functions such as memory， logic， and optical sensor based on 2D materials are vertically stacked on different layers. d-f Independent operation characteristics of memory (1st layer)， logic (2nd layer)， and optical sensor (3rd layer) located in each layer.

Fig. 10 a Overview of top layers suitable for placing sensor elements in vertically integrated structures. b， c Illustration and optical microscopy image of a vertically stacked inverter with a gate-sharing structure composed of pentacene and GZTO. d， e Response characteristics of the vertically stacked inverter according to a blue LED pulse. f Schematic diagram of the structure that connects the LED and the driving TFT， DNTT OTFT， through a laser drill. g Image showing the fabricated paper-based AM LED array. h Schematic diagram of a vertically stacked device of CNTFET and IGZO based CMOS inverter and temperature sensor on a flexible substrate. i Real-time temperature measurement according to human hand contact. j Illustration of an ammonia gas sensor device based on a vertically stacked SWCNT inverter. k Shift of output voltage curve of vertically stacked SWCNT inverter with ammonia gas concentration. l Vertically integrated structures of OPS and OTFT and their equivalent circuits. m Current density–voltage characteristic of OPS device according to light intensity and curve of measured EQE.

Fig. 11 a Illustration of a nanosystem consisting of four stacked layers with diferent functions such as silicon FET logic, CNTFET logic, RRAM, CNTFET sensor, and logic. b Detection of various gas components by changing the electrical properties of functionalized CNTFET gas sensors. c Organic ternary logic inverter in which fash memory and heterojunction transistors are vertically stacked in a via-hole-less metal interconnection scheme. d Optimization of the intermediate logic state of the ternary inverter according to fash memory state determined by the programming voltage. e Schematic illustration of the AM micro-LED display. f Luminance and current of 10–40 μm blue and green micro-LEDs with a 1T1D structure normalized by the area of the

micro-LED. g Optical microscope image of the QR code implemented with the high-resolution AM blue micro-LED display at a system level, consisting of 1,024 pixels. h Schematic diagram of TFT-driven full-color OLED with a structure in which red (R), green (G), and blue (B) units are vertically stacked. i Current-luminance characteristics of vertically stacked TFT-driven full-color OLEDs in which R, G, and B pixels. j Multi-color realization through R, G, and B combination of TFT-driven vertically stacked full-color

OLED

Fig. 12 An overview of 3D integration based on reliable metal interconnections and future applications of various semiconductor materials

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